1. Field of the Invention
The present invention relates to a defect estimation device and method used to estimate defects of a pattern formed on an object to be inspected such as a mask, and an inspection system and inspection method used to detect defects of a pattern formed on an object to be inspected.
2. Background Art
In recent years, as the levels of integration and capacity of large scale integrated circuits (LSIs) have increased, there has been a need to continue to reduce the width of the circuit patterns of semiconductor devices. Semiconductor devices are manufactured by a reduced projection exposure apparatus called a “stepper” using original artwork patterns with a circuit pattern formed thereon, these are called masks or reticles (hereinafter referred to collectively as masks). Specifically, a pattern on a mask is transferred to the wafer by exposure to light, thereby forming circuits on to a wafer. Masks used to transfer such fine circuit patterns to the wafer are manufactured by electron beam writing apparatuses, which can write micropatterns. Further, effort has been made to develop a laser beam writing apparatus, which uses a laser beam for writing. It should be noted that electron beam apparatuses are also used to directly write a circuit pattern on a wafer.
Incidentally, since the cost to manufacture LSIs is very high, an increase in yield is required to make the manufacturing economically feasible. Meanwhile, recent representative logic devices require a pattern having a line width of several ten nano-meters. Major factors that reduce the yield include a mask containing a pattern defect and a variation in conditions of the exposure transfer. In the prior art, with the miniaturization of an LSI pattern dimension to be formed on a semiconductor wafer, mask dimensional accuracy has been improved, by the variation margin of process terms and conditions having been absorbed. Therefore, in the mask inspection, the dimension of the pattern defect is miniaturized, and a positional error of an extremely small pattern is required to be inspected. Therefore, high inspection accuracy is required of inspection systems for detecting defects of masks used in LSI manufacture.
One of the factors that allow miniaturization of a mask pattern is the application of Resolution Enhancement Technology (herein after referred to as RET). In the RET technique, an auxiliary pattern referred to as an assist pattern is disposed on the side of a main pattern, whereby the formability of the main pattern is improved. Although the auxiliary pattern is not part of a transfer image, light energy entering a region of the main pattern is secured by the provision of the auxiliary pattern. In a mask inspection device, such a defect of the assist pattern can also be detected.
There are two known mask defect detecting methods: the die-to-die inspection method and the die-to-database inspection method. The die-to-die inspection method is used when the mask to be inspected has thereon a plurality of identical chip patterns, or a plurality of chip patterns each including an identical pattern segment. In this method, these identical chip patterns or identical pattern segments, which are to be printed to the wafer, are compared to each other. This method permits accurate inspection using a relatively simple system configuration, since patterns on the same mask are directly compared to each other. However, this method cannot detect a defect common to both compared patterns. In the die-to-database inspection method, on the other hand, an actual pattern on a mask is compared to reference data generated from the design pattern data that was used to manufacture the mask. Thus, this method allows exact comparison of the pattern with the design pattern data, although the required system size is large since the method requires a processing system for generating a reference image. There is no choice but to use this inspection method when the mask to be inspected has only one chip pattern to be transferred to the wafer.
In die-to-die inspection, light is emitted from a light source, and the mask to be inspected is irradiated with this light through an optical system. The mask is mounted on a table, and this table is moved so that the emitted beam of light scans the surface of the mask. Light transmitted through or reflected from the mask reaches an image sensor, thereby forming an image thereon. The optical image thus formed on the image sensor is sent to a comparing unit as measurement data. The comparing unit compares the measurement data with reference data in accordance with an appropriate algorithm, and if they are not identical, the mask is determined to have a defect (see Patent Document 1).
In the prior art inspection device, when it is determined that there is a defect, the optical image used as a basis for the determination and the corresponding reference image are stored in the inspection device along with the coordinates of these images. When the inspection of one mask is completed, an operator visually confirms a pattern at a defect portion utilizing an optical observation system in the inspection device. Then, the necessity of repair is determined. After a defect to be repaired is discovered the mask and the information required for the repair are sent to a repair device. The information required for the repair is a cut-out portion of pattern data for use in the recognition of coordinates in the mask, discrimination between extrusion and intrusion defects, discrimination whether to remove a light-shielding film or deposit a pattern at a portion to be repaired by the repair device.
As described above, in the prior art inspection device, a mask pattern image obtained by imaging an optical image by an image sensor is determined to be correct. However, with the recent miniaturization of a device pattern on a mask, it is difficult to distinguish a difference between a shape defect of a pattern and a potentially existing shape error of a pattern. Incidentally, defects associated with micropatterns include not only shape defects typified by pattern edge roughness, but also pattern linewidth errors and pattern displacement errors, which are becoming more and more significant due to the miniaturization of device patterns. Therefore, there has been a strong need to accurately control the dimensions of patterns, thus increasing the difficulty of manufacturing masks. As a result, there has been a loss in the yield of masks that meet the required specifications, thereby raising mask manufacturing cost. Further, the required accuracy of a linewidth or pattern of a mask increases, whereby determination as to whether or not there is a defect is difficult if the only comparison is between generated reference data based on design pattern data and a pattern image taken by an inspection device.
In order to address this problem, a defect evaluating method has been proposed which uses a simulation. This method simulates the image which would be printed from the mask to a wafer by the photolithography apparatus and determines whether or not the pattern on the mask is defective by inspecting the simulated image. Non-Patent Document 1 shows a method of capturing an inspected mask image by a CCD (Charge Coupled Device), using a high-resolution optical system and a method of obtaining a wafer aerial image by using a low-resolution optical system (see, FIG. 1). In the former method, the mask image of the inspected pattern and the reference pattern is acquired by the high-resolution optical system. A wafer transfer image is estimated from the mask image through the process of FIG. 2. Thereafter, the wafer transfer images are compared with each other and defect determination is performed. Meanwhile, in the latter method, the wafer transfer image is directly collected by an optical wafer transfer device. In these methods, an image to be transferred onto a wafer is predicted, and the defect determination is performed based on the image. The latter method is also described in Non-Patent Document 2 (see, FIG. 3 and the bottom of page 3).
When a plurality of fractures and taper shaped defects occur in an assist pattern corresponding to a certain part of the main pattern on a mask, the shape of the main pattern in an estimated wafer transfer image should be in such a state that a dimensional error such as constriction of the line width occurs. That is to say, according to a determination method based on a transfer image, it can be predicted that the shape defect of a mask makes the transfer image incorrect. However, in this case, there is a problem that it cannot be indicated which of the defect portions in the assist pattern, that is, which of a plurality of fracture portions causes the constriction of the line width in the main pattern, or which combination of the plurality of fracture portions causes the constriction of the line width in the main pattern.
Patent Document 2 discloses a method for simulating a lithographic design comprised of a number of polygons arranged in a predetermined configuration. Specifically, referring to FIG. 4 of this publication, an aerial image is generated using a bitmap image available from the polygon design database (box 126), and resist modeling or simulation is performed using this aerial image (box 128). FIG. 7 shows a technique of estimating a wafer pattern aerial image by simulation of an image from a mask inspection device. This technique indicates whether a wafer aerial image or a wafer image, obtained through a wafer generation process such as reaction of photoresist by light exposure, is correct.
Further, Patent Document 3 states as follows: “In any mask inspection system, the important decision to make is whether a given defect will ‘print’ on the underlying photoresist in a lithography process under specified conditions. If a mask defect does not print or have other effect on the lithography process, then the mask with the defect can still be used to provide acceptable lithography results. Therefore, one can avoid the expense in time and cost of repairing and/or replacing masks whose defects do not print.”
Patent Document 3 discloses a method of acquiring a defect area image including an image of a portion of a mask and generating a simulated image. This simulated image includes a simulation of an image which would be printed on the wafer.
As described above, according to the prior art inspection device, an estimated transfer image that would be transferred to the wafer including defects acquired by the inspection device can be generated. However, in the prior art there is no inspection device which can indicate the level of influence that a defect will have on the wafer. Furthermore, there is no inspection device that can determine whether the repair of a specific pattern error or repair of a combination of pattern errors in the wafer transfer image will result in an acceptable transfer image to the wafer. For example, when a pattern is formed on the wafer using an exposure light source having a directivity in irradiation intensity, a irradiation direction and a mask pattern that have been optimized, a minute pattern can be transferred onto the wafer in combination with the exposure light. Estimation is then required to determine which portion of the wafer transfer image is affected by the mask shape defect using accurate simulation including a light source.    [Patent Document 1] Japanese laid-open Patent publication No. 2008-112178    [Patent Document 2] Japanese laid-open Patent publication No. 2009-105430    [Patent Document 3] Published Japanese translation of PCT application No. 2001-516898    [Non-Patent Document 1] Carl Hess et al. (KLA-Tencor Corporation), A Novel Approach: High Resolution Inspection with a Wafer Plane Defect Detection. Prof of SPIE Vol. 7028, 70281F    [Non-Patent Document 2] Dan Ros et al. (MP-Mask Technology Center) Qualification of Aerial Image 193 nm Inspection Tool for All Masks and All Process Steps, Proc of SPIE Vol. 7028, 70282Q (2008)    [Non-Patent Document 3] (H. H. Hopkins, On the di_reaction theory of optical images, In Proc. Royal Soc. Series A., volume 217 No. 1131, pages 408-432, 1953).    [Non-Patent Document 4] (N. B. Cobb, A. Zakhor, M. Reihani, F. Jahansooz, and V. N. Raghavan: Proc. SPIE 3051 (1997) 458).    [Non-Patent Document 5] (M. Osawa, T. Yao, H. Aoyama, K. Ogino, H. Hoshino, Y. Machida, S. Asai, and H. Arimoto, J. Vac. Sci. Technol. B21 (2003) 2806).    [Non-Patent Document 6] N. B Cobb, (Fast Optical and Process Proximity Correction Algorithms for Integrated Circuit Manufacturing) A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor Of Philosophy in Engineering: Electrical Engineering and Computer Science in the Graduate Division of the University of California in Berkeley, Spring 1988 can be referred to.
The present invention has been conceived in view of the above problem. Therefore, an object of this invention is to provide a defect estimation device and a defect estimation method, which can estimate a defect or a plurality of defects on a mask, the influence of the defect on a wafer, and the degree of improvement by repair.
Further, an object of this invention is to provide an inspection device which estimates a defect on a mask, the influence of the defect on a wafer and the degree of improvement by repair, thereby indicating the level of influence of the mask defect itself on the wafer and the portion of the pattern on the mask to be repaired for eliminating a detected defect.
Furthermore, another object of this invention is to provide an inspection device and an inspection method, which can facilitate a defect determination processing for a mask and can perform defect determination processing and estimate a defect or a plurality of defects on a mask and the resultant influence on a wafer image.
Other challenges and advantages of the present invention are apparent from the following description.